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1 for more information www.linear.com/ltc3607 run1 run2 sw2 ltc3607 v in 12v 10f 2 10f 121k 10f 121k 4.7h 4.7h 887k 549k v out1 5v at 600ma v out2 3.3v at 600ma 3607 ta01a sv in 22pf 22pf sw1 gnd v fb1 v fb2 pv in2 pv in1 typical a pplica t ion fea t ures descrip t ion dual 600ma 15v monolithic synchronous step-down dc/dc regulator the ltc ? 3607 is a 15v dual 600ma monolithic synchro - nous step-down regulator which has only 55a quiescent cur r ent. intended for a variety of applications, including dual lithium-ion battery products, it operates from a wide 4.5v to 15v input voltage range. it features a constant 2.25mhz switching frequency, enabling the use of tiny, low cost capacitors and inductors 1mm or less in height. each output voltage is adjustable from 0.6v to v in . the internal synchronous power switches provide high ef - fciency without the need for external schottky diodes. a u se r s electable mode input is provided to allow the user to trade off ripple noise for light load effciency; burst mode operation provides the highest effciency at light loads, while pulse-skipping mode provides the lowest ripple noise. to further the maximize battery run time, the p-channel mosfets are turned on continuously in dropout (100% duty cycle). in shutdown, the device draws <1a. a pplica t ions n high effciency: up to 96% n very low quiescent current: 55a total n 2.25mhz constant frequency operation n low dropout operation: 100% duty cycle n low-ripple (typical 30mv p-p ) burst mode ? operation n peak current-mode control architecture for excellent lin e and load transient response n wide voltage input range: 4.5v to 15v n 600ma/channel rated output current n 0.6v reference allows low output voltages n 1.5% output voltage accuracy n ultralow shutdown current: i q < 1a n internal compensation n power good outputs n externally frequency synchronization (1mhz to 4mhz) n independent internal soft-start for each channel n small 16-lead thermally enhanced thin qfn (3m m 3mm) and mse packages n dual lithium-ion battery supplies n automotive applications n servers l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. effciency and power loss vs load current load current (ma) efficiency (%) power loss (w) 3607 ta01b 100 90 0.1 1 0.01 0.001 80 60 50 40 30 20 10 70 0 1 100 1000 10 v in = 12v v out = 5v v out = 3.3v ltc3607 3607fb
2 for more information www.linear.com/ltc3607 p in c on f igura t ion a bsolu t e maxi m u m r a t ings pv in , sv in voltages .................................... C0.3v to 15v run1, run2 voltages ................. C0. 3v to (sv in + 0.3v) v fb1 , v fb2 voltages ................................... C0. 3v to 3.6v mode/sync voltage ................................. C0.3v to 3.6v pgood1, pgood2 voltages ...................... C0.3v to 15v (note 1) 16 15 14 13 5 6 7 8 top view ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1 mode/sync pgood1 sv in pgnd1 sgnd pgood2 sgnd pgnd2 run1 v fb1 v fb2 run2 sw1 pv in1 pv in2 sw2 17 pgnd t jmax = 125c, ja = 68c/w, jc = 7.5c/w exposed pad (pin 17) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 sv in pgnd1 sw1 pv in1 pv in2 sw2 pgnd2 sgnd 16 15 14 13 12 11 10 9 pgood1 mode/sync run1 v fb1 v fb2 run2 sgnd pgood2 top view 17 pgnd mse package 16-lead plastic msop t jmax = 125c, ja = 37c/w, jc = 10c/w exposed pad (pin 17) is pgnd, must be soldered to pcb lead free finish tape and reel part marking* package description temperature range ltc3607eud#pbf ltc3607eud#trpbf lfnb 16-lead (3mm 3mm) plastic qfn C40c to 125c (note 2) ltc3607iud#pbf ltc3607iud#trpbf lfnb 16-lead (3mm 3mm) plastic qfn C40c to 125c (note 2) ltc3607emse#pbf ltc3607emse#trpbf 3607 16-lead plastic msop C40c to 125c (note 2) ltc3607imse#pbf ltc3607imse#trpbf 3607 16-lead plastic msop C40c to 125c (note 2) consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. f or m o re information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 7) ............................................ C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) msop package ................................................. 300 c o r d er i n f or m a t ion ltc3607 3607fb
3 for more information www.linear.com/ltc3607 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units sv in operating voltage range l 4.5 15 v pv in operating voltage range l 4.5 15 v v out output voltage range 0.6 pv in v v fb feedback voltage (note 3) l 0.591 0.588 0.6 0.6 0.609 0.6 1 2 v v i fb feedback pin input current 30 na v line reg reference voltage line regulation v in = 4.5v to 15v (note 3) 0.1 0.15 %/v v load reg output voltage load regulation mode/sync = 0v (note 3) 0.5 % i s input dc supply current active mode sleep mode (both channels) sleep mode (single channel) shutdown (not e 4) v fb1 = v fb2 = 0.5v v fb1 = v fb2 = 0.64v v fb(1 or 2) = 0.64v run1 = run2 = 0v 3.2 55 35 0.1 90 60 1 ma a a a f osc oscillator frequency v fb1, 2 = 0.6v l 1.8 2.25 2.7 mhz f sync synchronization frequency 1.0 4.0 mhz i lim peak switch current limit v fb1, 2 = 0.5v, duty cycle < 35% 0.75 1 1.25 a r ds(on) top switch on-resistance bottom switch on-resistance (no t e 6) (note 6) 0.6 0.25 uvlo sv in undervoltage lockout threshold sv in rising 3.4 4.3 v pgood pgood1/2 overvoltage threshold v fb1, 2 rising v fb1, 2 hysteresis 8.5 C3 11 % % pgo o d1/2 undervoltage threshold v fb1, 2 ramping down v fb1, 2 hysteresis C11 C8.5 3 % % pgoo d 1/2 on-resistance channel 1 or channel 2 active run1 = run2 = 0v 70 700 t pgood power good blanking time 64 cycles i pgood pgood leakage 1 a v run run1/2 v il run1/2 v ih l l 0.55 3.0 v v i run run1/2 leakage current l 0.01 1 a v mode/sync mode/sync v il mode/sync v ih l l 0.3 1.0 v v t softstart internal soft-start time v fb from 10% to 90% full scale pv in1 = pv in2 = sv in = 4.5v 0.35 ms the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c. v in = 12v, unless otherwise specifed. (note 2) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the ltc3607 is tested under pulsed load conditions such that t j t a . the ltc3607e is guaranteed to meet specifcations from 0c to 85c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3607i is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d ? ja c/w) where ja is the package thermal impedance. note that the maximum ambient temperature is consistent with these specifcations determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3. the ltc3607 is tested in a proprietary test mode that connects v fb to the output of the error amplifer to an external servo loop. note 4. dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5. t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (pd ? ja ). note 6. the qfn switch on-resistance is guaranteed by correlation to wafer level measurements. note 7. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active continuous operation above the specifed maximum operating junction temperature may impair device reliability. ltc3607 3607fb
4 for more information www.linear.com/ltc3607 typical p er f or m ance c harac t eris t ics effciency vs input voltage burst mode operation burst mode operation pulse-skipping mode load step in burst mode operation start-up (burst mode operation) v out short to gnd (burst mode operation) effciency vs load current burst mode operation effciency vs load current burst mode operation effciency vs load current t a = 25c, unless otherwise noted. load current (ma) efficiency (%) 3607 g01 100 90 80 60 50 40 30 20 10 70 0 0.1 1 100 1000 10 v out = 2.5v v in = 5v v in = 8.4v v in = 12v load current (ma) efficiency (%) 3607 g02 100 90 80 60 50 40 30 20 10 70 0 0.1 1 100 1000 10 v out = 3.3v v in = 5v v in = 8.4v v in = 12v v in = 8.4v v out = 2.5v i load = 30ma to 600ma v out 100mv/div i l 200ma/div 3607 g07 20s/div v in = 8.4v v out = 2.5v i load = 20ma run 2v/div pgood 2v/div v out 2v/div i l 0.5a/div 3607 g08 200s/div input voltage (v) efficiency (%) 3607 g04 100 95 90 80 75 70 65 60 55 85 50 4 6 12 14 16 108 i load = 1ma i load = 10ma i load = 100ma i load = 600ma v out = 3.3v v in = 8.4v v out = 2.5v i load = 0a pgood 2v/div v out 1v/div i l 1a/div 3607 g09 100s/div v in = 8.4v v out = 2.5v i load = 100ma sw 5v/div i l 200ma/div v out 50mv/div 3607 g05 2s/div v in = 8.4v v out = 2.5v i load = 20ma sw 5v/div i l 200ma/div v out 50mv/div 3607 g06 2s/div load current (ma) efficiency (%) 3607 g03 100 90 80 60 50 40 30 20 10 70 0 0.1 1 100 1000 10 v in = 8.4v v out = 5v burst mode operation pulse skip ltc3607 3607fb
5 for more information www.linear.com/ltc3607 typical p er f or m ance c harac t eris t ics r ds(on) vs input voltage r ds(on) vs temperature load regulation line regulation oscillator frequency vs temperature reference voltage vs temperature t a = 25c, unless otherwise noted. temperature (c) ?50 frequency variation (%) 2 0 ?2 ?4 ?6 ?8 ?10 ?12 3607 g10 125 0 50 ?25 25 75 100 switch leakage vs temperature peak current limit vs temperature v in (v) 4 ?v out /v out error (%) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 3607 g15 16 8 10 6 12 14 temperature (c) ?50 v fb (v) 0.605 0.603 0.601 0.599 0.597 0.595 3607 g11 125 0 50 ?25 25 75 100 v in = 12v temperature (c) ?50 peak current limit (ma) 1200 1150 1100 1050 1000 950 900 3607 g16 125 0 25 ?25 50 75 100 v in = 12v temperature (c) ?50 leakage current (na) 7000 6000 5000 4000 3000 2000 1000 0 3607 g14 150 250 50 ?25 75 100 125 top switch bottom switch v in = 12v v in (v) 4 r ds(on) () 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3607 g12 16 8 10 6 12 14 top switch bottom switch temperature (c) ?50 r ds(on) () 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3607 g13 125 0 50 ?25 75 100 v in = 12v top switch bottom switch load current (ma) 0 ?v out /v out (%) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 3607 g17 600 200100 300 400 500 pulse skip burst mode operation v out = 3.3v ltc3607 3607fb
6 for more information www.linear.com/ltc3607 p in func t ions pv in1 , pv in2 , sv in (pins 6, 7, 3/pins 4, 5, 1): main power supply. must be closely decoupled to gnd. these inputs may each be powered from different supply voltages. connect sv in to either pv in1 or pv in2 , whichever one is higher. for applications where its not known which pv in(1 or 2) is higher, connect external diodes between sv in to both pv in1 and pv in2 to ensure that sv in is less than a diode drop from the higher of pv in1 or pv in2 . pgnd1, pgnd2, sgnd, pgnd (pins 4, 9, 10, 12, exposed pad pin 17/pins 2, 7, 8, 10, exposed pad pin 17): main ground. connect to the (C) terminals of c out1 , c out2 , and c in . the exposed pad must be soldered to pcb ground for electrical contact and rated thermal performance. all sgnd and pgnd pins must be externally connected to ground. v fb1 (pin 15/pin 13): regulator 1 output feedback. receives the feedback voltage from the external resistor divider across the regulator 1 output. nominal voltage for this pin is 0.6v. sw1 (pin 5/pin 3): regulator 1 switch node connection to the inductor. this pin switches from pv in1 to pgnd1. run1 (pin 16/pin 14): regulator 1 enable. forcing this pin high (above 3v) enables regulator 1, while forcing it to sgnd causes regulator 1 to shut down. it is possible to use a 3.3v source to drive this pin, or tie it to sv in . an internal soft-start limits the rise time to a minimum of 0.35ms. pgood1 (pin 2/pin 16): regulator 1 power good. this common-drain logic output is pulled to sgnd when the channel 1 output voltage is not within 8.5% of regulation. v fb2 (pin 14/pin 12): regulator 2 output feedback. receives the feedback voltage from the external resistor divider across the regulator 2 output. nominal voltage for this pin is 0.6v. sw2 (pin 8/pin 6): regulator 2 switch node connection to the inductor. this pin switches from pv in2 to pgnd2. run2 (pin 13/pin 11): regulator 2 enable. forcing this pin high (above 3.0v) enables regulator 2, while forcing it to sgnd causes regulator 2 to shut down. it is possible to use a 3.3v source to drive this pin, or tie it to sv in . an internal soft-start limits the rise time to a minimum of 0.35ms. pgood2 (pin 11/pin 9): regulator 2 power good. this common-drain logic output is pulled to sgnd when the channel 2 output voltage is not within 8.5% of regulation. mode/sync (pin 1/pin 15): combination mode selec - tion and oscillator synchronization. this pin controls the lig h t-load behavior of the device. forcing this pin to sgnd selects pulse-skipping mode. floating this pin or forcing it above 1v selects burst mode operation. the internal oscillation frequency can be synchronized to an external oscillator applied to this pin and pulse-skipping mode is automatically selected. (qfn/mse) ltc3607 3607fb
7 for more information www.linear.com/ltc3607 b lock diagra m control logic ? + ? + ? + level shift hv icmp pv in1 sw1 pgnd1 pgood1 pv in2 sw2 pgnd2 pgood2 3607 bd mode/sync rcmp hv level shift osc ldo 3.3v 0.65v bandgap reference 0.55v 0.6v clk mode 3.3v 3m pgood1 0.55v run1 sgnd run2 v fb1 i th sv in v fb2 uvcomp ea ovcomp 0.6v 0.65v regulator 1 regulator 2 (identical to regulator 1) ltc3607 3607fb
8 for more information www.linear.com/ltc3607 o pera t ion the ltc3607 uses a constant-frequency, peak current mode architecture. the operating frequency is set at 2.25mhz and can be synchronized to an external oscillator between 1mhz and 4mhz. both channels share the same clock and run in-phase. to suit a variety of applications, the selectable mode/sync pin allows the user to trade- off ripple for effciency. the output voltage is set by an external divider returned to the v fb pins. an error amplifer compares the divided output voltage with a reference voltage of 0.6v and ad - justs the peak inductor current accordingly. overvoltage an d un de rvoltage comparators will pull the independent pgood outputs low if the output voltage is not within 8.5%. the pgood outputs will go high 64 clock cycles after achieving regulation and will go low 64 cycles after falling out of regulation. whether in burst mode or pulse-skipping operation, the overvoltage protection circuit is still enabled when the rest of the regulator is asleep. hence, if v out rises above the overvoltage threshold, the regulator is forced out of sleep. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the reference voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor fows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the p e ak inductor current is controlled by the internally compensated ith voltage, which is the output of the error amplifer. this amplifer compares the v fb pin to the 0.6v internal reference. when the load current increases, the v fb voltage decreases slightly below the reference. this decrease causes the error amplifer to increase the ith voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low current operation two discontinuous-conduction modes (dcms) are avail - able to control the operation of the ltc3607 at low output curr ents. both modes, burst mode operation and pulse- skipping, automatically switch from continuous operation to the selected mode when the load current is low. to optimize effciency, burst mode operation can be se - lected by foating the mode/sync pin or setting it to 1v o r gr e ater. when the load is relatively light, the ltc3607 automatically switches into burst mode operation in which the pmos switch operates intermittently based on load demand with a fxed peak inductor current. by running cycles periodically, the switching losses, which are domi - nated by the gate charge losses of the power mosfets, are mi nimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. a voltage comparator trips when the ith voltage drops below an internal clamp voltage, shutting off the switch and reducing the power. the output capacitor and the inductor supply the power to the load until ith exceeds an internal clamp voltage, turning on the switch and the main control loop, which starts another cycle. to optimize ripple, pulse-skipping mode can be selected by grounding the mode/sync pin. in the ltc3607, pulse- skipping mode is implemented similarly to burst mode operation with the ith clamp set to a lower internal clamp voltage. this results in lower ripple than in burst mode operation with the trade-off being slightly lower effciency. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. ltc3607 3607fb
9 for more information www.linear.com/ltc3607 a pplica t ions i n f or m a t ion an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3607 is used at 100% duty cycle with low input voltage (see thermal considerations in the applica - tions information section). low/high supply operation the ltc 3607 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 3.7v to prevent unstable operation. a general ltc3607 application circuit is shown in figure 1. external component selection is driven by the load require - ment, and begins with the selection of the inductor l. once the i n ductor is chosen, c in and c out can be selected. inductor selection the operating frequency directly effects both the inductor value, and the ripple current. the inductor ripple current i l decreases with higher frequency and/or inductance and increases with higher v in : ?i l = v out f o ? l ? 1? v out v in ? ? ? ? accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is i l t* o(max) , where i o(max) is the maximum rated output current. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a specifed maximum, the inductor value should be chosen according to the following equation: l = v out f o ? i l ? 1? v out v in(max) ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this transition to occur at lower load currents. this causes a dip in effciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar elec - trical characteristics. the choice of which style inductor to use of ten depends more on the price vs size requirements and any radiated feld/emi requirements than on what the ltc3607 requires to operate. table 1 shows the websites of several surface mount inductor manufacturers. table 1. inductor manufacturer coilcraft http://www.coilcraft.com/powersel_lowl.html cooper bussmann http://www.cooperindustries.com/content/public/ en/bussmann/electronics/products/coiltronics_ inductorandtransformermagnetics.html wrth electronic http://katalog.we-online.com/en/pbs/browse/ power-magnetics/speicherdrosseln murata http://www.murata.com/products/inductor/index. html tdk http://www.tdk.co.jp/tefe02/coil.htm vishay http://www.vishay.com/inductors/power- inductors/ sumida http://www.sumida.com/en/products/ power_main.php ltc3607 3607fb
10 for more information www.linear.com/ltc3607 a pplica t ions i n f or m a t ion input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms i out(max) v out (v in C v out ) v in where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur - rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple cur - rent ratings are often based on only 2000 hours lifetime. this ma kes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple (v out ) is determined by: v out ? ?i l esr+ 1 8f o c out ? ? ? ? where f o = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 240ma the output ripple will be less than 100mv at maximum v in and f o = 2.25mhz with: esr cout < 150m. once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the frst cycle does the output drop linearly. the output droop, v droop , is usually about fve times the linear drop of the frst cycle. thus, a good place to start is with the output capacitor size of approximately: c out 5 ?i out f o ? v droop though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. ceramic input and output capacitors high value, low cost ceramic capacitors are available in small case sizes. their high ripple current, high voltage rating, and low esr make them ideal for switching regulator applications. however, due to the self-resonant and high-q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. for a more detailed discussion, refer to application note 88. ltc3607 3607fb
11 for more information www.linear.com/ltc3607 a pplica t ions i n f or m a t ion setting the output voltage the ltc3607 develops a 0.6v reference voltage between the feedback pins, v fb1 and v fb2 , and ground as shown in figure 1. the output voltage is set by a resistive divider according to the following formula: v out =0.6v 1+ r1 r2 ? ? ? ? ? ? keeping the current small (<5a) in these resistors maxi - mizes effciency, but making them too small may allow str a y capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward ca - pacitor c ff may also be used. great care should be taken to route the v fb traces away from noise sources, such as the inductor or the sw traces. for continuous mode operation with a fxed maximum input voltage, the minimum value that the output voltage can be reduced to is set by the minimum on-time, which is approximately 65ns. for fxed frequency (2.25mhz) ap - plications, the relation between minimum output voltage and max imum input voltage is: v out(min) = 0.14625 ? v in(max) if the output voltage drops below that limit, the output will still regulate, but the part will skip cycles. power good outputs the pgood1 and pgood2 are open-drain outputs which pull low when a regulator is out of regulation. when the output voltage is within 8.5% of regulation, a timer is started which releases the relevant pgood pin after 64 clock cycles. mode selection & frequency synchronization the mode/sync pin is a multipurpose pin which provides mode selection and frequency synchronization. floating this pin or connecting it to a 3.3v source enables burst mode operation, which provides optimal light load effciency at the cost of a slightly higher output voltage ripple. when this pin is connected to ground, pulse-skipping operation is selected. this mode provides the lowest output ripple, at the cost of slightly lower light load effciency. the ltc3607 can also be synchronized to another ltc3607 by the mode/sync pin. during synchronization, the mode is set to pulse-skipping and the top switch turn-on is synchronized to the rising edge of the external clock. pulse-skipping mode is also the default mode during star t-up. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or dis - charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feed-forward capacitor can be added to improve the high frequency response, as shown in figure 1. capacitors c1 and c2 provide phase lead by creating high frequency zeros with r1 and r3 respectively, which improve the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in paral - lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifcally for this purpose and usually incorporates cur - rent limiting, short-circuit protection, and soft-starting. ltc3607 3607fb
12 for more information www.linear.com/ltc3607 effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %eff ciency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the ci rcuit produce losses, four main sources usually account for most of the losses in ltc3607 circuits: 1) v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) th e v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continu - ous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current fows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 C d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 4) other hidden losses such as copper trace and internal battery resistances can account for additional effciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3607 does not dis - sipate much heat due to its high effciency. however, in app l ications where the ltc3607 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches for each channel will be turned off and the sw nodes will become high impedance. to prevent the ltc3607 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient a pplica t ions i n f or m a t ion ltc3607 3607fb
13 for more information www.linear.com/ltc3607 as an example, consider the case when the ltc3607 is in dropout on both channels at an input voltage of 5v with a load current of 600ma and an ambient temperature of 25c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the main switch is 0.9. therefore, power dissipated by each channel is: p d = i 2 ? r ds(on) = 324mw running the two regulator channels under the same con - ditions will result in a total power dissipation of 0.648w. t he m s e package junction-to-ambient thermal resistance, ja , is 37c/w. therefore, the junction temperature of the regulator operating in a 25c ambient temperature is approximately: t j = 0.648w ? 37c/w + 25c = 49c design example as a design example, consider using the ltc3607 in a portable application with a dual lithium-ion battery. the battery provides a v in = 5.6v to 8.4v. the loads require a maximum of 600ma in active mode and 2ma in standby mode. the output voltages are v out1 = 3.3v and v out2 = 2.5v. since the load still needs power in standby, burst mode operation is selected for good light load effciency. first, calculate the inductor values for about 240ma ripple current at maximum v in : l1= 3.3v 2.25mhz ? 240ma ? 1? 3.3v 8.4v ? ? ? ? = 3.7h choosing the closest standardized inductor value of 3.3h results in a maximum ripple current of: ?i l1 = 3.3v 2.25mhz ? 3.3h ? 1? 3.3v 8.4v ? ? ? ? =270ma the same calculations for l2 result in a standard inductor value of 3.3h and a maximum current ripple of 236ma. for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c out1 5 ? 600ma 2.25mhz ? (5% ? 3.3v) = 8.1 f c out2 5 ? 600ma 2.25mhz ? (5% ? 2.5v) =10.7 f for both outputs, a close standard value is 10f. since the output impedance of a lithium-ion battery is very low, each c in is chosen to be 10f also. the output voltages can now be programmed by choosing the values of r1 thru r4. to maintain high effciency, the current in these resistors should be kept small. choosing 5a with the 0.6v feedback voltage makes r2 and r4 ~ 120k. close standard 1% resistor values is 121k and then r1 and r3 are 549k and 383k, respectively. the pgood pins are common drain outputs, thus requir - ing pull-up resistors. two 100k resistors are used for ad equ a te speed. figure 1 shows the complete schematic for this design example. the specifc passive components chosen allow for a 1mm height power supply that maintains a high ef - fciency across load. board layout considerations w he n l aying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3607. these items are also illustrated graphically in the layout diagram of figure 2. check the following in your layout: 1. do the i nput capacitors c in connect to pv in1 , pv in2 , pgnd1, and pgnd2 as closely as possible? these ca - pacitors provides the ac current to the internal power mos fe t s and their drivers. 2. are c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . a pplica t ions i n f or m a t ion ltc3607 3607fb
14 for more information www.linear.com/ltc3607 3. the resistor divider formed by r1 and r2 must be con nected between the (+) plate of c out and a ground sense line terminated near gnd (exposed pad). the feedback signals v fb1 and v fb2 should be routed away from noisy components and traces (such as the sw lines) and their traces should be minimized. 4. keep s ensitive components away from the sw pins. the feedback resistors r1 to r4 should be routed away from the sw traces and the inductors. a pplica t ions i n f or m a t ion figure 1. design example circuit figure 2. example of power component layout for qfn package figure 3. example of power component layout for mse package v out2 v out1 v in 3607 f03 via to v in pin 1 vias to ground plane vias to ground plane c in c in c out2 c out1 l l 17 5. a ground plane is preferred, but if not available keep the s ignal and power grounds segregated with small signal components returning to the gnd pin at one point. additionally, the two grounds should not share the high current paths of c in or c out . 6. flood a ll unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to v in or gnd. refer to figures 2 and 3 for board layout examples. mode/sync run1 run2 run2 run1 sw1 sw2 ltc3607 pgnd2 pgnd1 gnd sgnd 3607 f01 c in1 10f v in 8.4v c in2 10f pv in1 sv in pv in2 v fb1 v out1 3.3v at 600ma 100k 100k r4 121k 1% c out2 10f v out2 2.5v at 600ma l1 3.3h l2 3.3h pgood2 v fb2 r2 121k 1% c1: tdk c2012x5r1c106k/1.25 c out1 , c out2 : c2012x5r0j106k/1.25 l1, l2: wrth elektronik 744025003 c1, 22pf c2, 22pf r3, 383k 1% pgood1 r1, 549k 1% c out1 10f v out1 v out2 v in 3607 f02 via to v in gnd vias to ground plane vias to ground plane vias to ground plane c out1 c in c in gnd c out2 l l 1 2 12 11 3 4 10 9 5 6 7 8 16 15 14 13 17 ltc3607 3607fb
15 for more information www.linear.com/ltc3607 typical a pplica t ions low output voltage and main supply 5v/2.5v 2.25mhz buck regulator mode/sync run1 run1 run2 run2 sw1 pgood1 sw2 pgood2 ltc3607 pgnd2 pgnd1 gnd sgnd 3607 ta02 c in1 10f v in 6v to 15v v out1 5v at 600ma c in2 10f pv in1 sv in pv in2 100k 100k l1: sumida cdrh3d16/hpnp-4r7nc l2: sumida cdrh3d16/hpnp-3r3nc v fb1 v out2 2.5v at 600ma l1, 4.7h l2, 3.3h v fb2 c out1 10f r2 121k 1% c out2 10f r4 121k 1% r3 383k 1% r1 887k 1% c1, 22pf c2, 22pf mode/sync run1 run1 pgood1 run2 pgood2 sw1 sw2 ltc3607 pgnd2 pgnd1 gnd sgnd c in 10f v in 12v pv in1 sv in pv in2 v fb1 v out2 1v at 600ma v out1 5v at 400ma l1 4.7h l2 1.5h v fb2 1000pf 100k 3607 ta03 c out1 10f l1: vishay ihlp1616bzer4r7m11 l2: vishay ihlp1616aber1r5m11 r2 121k 1% c out2 22f r4 121k 1% r3 80.6k 1% r1 887k 1% c1, 22pf c2, 22pf ltc3607 3607fb
16 for more information www.linear.com/ltc3607 typical a pplica t ions sequenced power supplies run1 pgood1 run2 mode/sync pgood2 sw1 v fb2 ltc3607 pgnd2 pgnd1 gnd sgnd 3607 ta04 c in1 10f v out1 100k v in 4.5v to 15v v out1 3.3v at 600ma c in2 10f 1000pf pv in1 sv in pv in2 v fb1 c out1 10f l1, l2: tdk vlcf4018t-3r3n1r2-2 r2 121k 1% r1 549k 1% c1, 22pf c out2 10f v out2 2.5v at 600ma r4 121k 1% r3 383k 1% c2, 22pf l2, 3.3h l1, 3.3h sw2 ltc3607 3607fb
17 for more information www.linear.com/ltc3607 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691 rev ?) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltc3607 3607fb
18 for more information www.linear.com/ltc3607 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) ltc3607 3607fb
19 for more information www.linear.com/ltc3607 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 11/13 clarifed run 1/2 voltages clarifed electrical table clarifed pin function descriptions 2 3 6 b 8/14 clarifed ripple feature clarifed electrical characteristics table clarifed output voltage formula 1 3 11 ltc3607 3607fb
20 for more information www.linear.com/ltc3607 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2013 lt 0814 rev b ? printed in usa v fb1 v fb2 run1 sw1 run2 sw2 ltc3607 gnd 3607 ta05 c in 10f 2 v in 5.6v to 8.4v sv in pv in1 pv in2 v out1 1.8v at 600ma c in : tdk c2012x5r1c106k/0.85 c out1 , c out2 : tdk c2012x5r0ji06k/0.85 l1: murata lqm2hpn2r2mgs l2: murata lqm2hpn3r3mgs v out2 3.3v at 600ma l1, 2.2h l2, 3.3h c out1 10f r2 121k r1 243k c1, 22pf c out2 10f r4 121k r3 549k c2, 22pf r ela t e d p ar t s typical a pplica t ion part number description comments ltc3601 15v, 1.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% e f fciency, v in : 4.5v to 15v, 3mm 3mm qfn-16, msop-16e ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% e f fciency, v in : 4.5v to 15v, 4mm 4mm qfn-20, msop-16e ltc3633 15v, dual 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% e f fciency, v in : 3.6v to 15v, 4mm 5mm qfn-28, tssop-28e ltc3605 15v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% e f fciency, v in : 4v to 15v, 4mm 4mm qfn-24 ltc3604 15v, 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% e f fciency, v in : 3.6v to 15v, 3mm 3mm qfn-16, msop-16e ltc3417a-2 5.5v, dual 1.5a/1a, 4mhz, synchronous step-down dc/dc converter 95% e f fciency, v in = 2.3v, 3mm 5mm dfn-16, tssop-16e ltc3407a /-2 5.5v, dual 600ma/600ma 1.5mhz, synchronous step-down dc/dc converter 95% e f fciency, v in = 2.5v, 3mm 3mm dfn-10, ms-10e ltc3419/-1 5.5v, dual 600ma/600ma 2.25mhz, synchronous step-down dc/dc converter 95% e f fciency, v in = 2.5v, 3mm 3mm dfn-10, ms-10 ltc3548a-1/-2 5.5v, dual 400ma and 800ma i out , 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in = 2.5v, 3mm 3mm dfn-10, ms-10e ltc3547/ ltc3547b 5.5v, dual monolithic 300ma, 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in = 2.5v, i q = 40a, i sd < 1a, 3mm 2mm dfn-8 ltc3 6 21 17v, 1a (i out ), 2.25mhz synchronous step-down dc/dc converter with 3.5a i q 95% effciency, v in = 2.7v to 17v, 3mm 2mm dfn-6, ms-8e 1mm height, 1.8v/3.3v buck regulator using chip inductors 10mm 3607 ta06 11mm c out1 c out2 v out1 v out2 l1 l2 v in c in c in gnd gnd via to v in 1 2 3 4 5 6 7 8 17 12 11 10 9 c1 r2 r1 c2 r4 r3 16 15 14 13 via to v out1 via to v out2 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3607 ltc3607 3607fb

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